LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity ffd is
port(
  clr: in std_logic;
  ck: in std_logic;
  d: in std_logic;
  e:in std_logic;
  q: out std_logic;
  nq: out std_logic );
end;


architecture beh of ffd is
begin
  process ( ck , clr )
  begin
    if clr ='1' then
      q <= '0' ;
      nq <='1';
    elsif ck'event and ck='1' then
      if e='1' then
        q <= d ;
        nq <= not d;
      end if;
    end if ;
  end process ;

end;

